1. Field of the Invention
This invention relates to semiconductor memory devices and to a method of manufacturing the same. In particular, it relates to non-volatile semiconductor memories having a floating gate and control gate and to a method of forming the same.
2. Description of the Related Art
To write data into an EPROM memory cell, the control gate is given a high positive voltage to form a channel in the substrate surface, and a positive voltage is applied to the drain. When this is done, the electrons running in the channel receive high energy from the high electric field that is generated in particular in the neighbourhood of the drain, with the result that they cross the energy barrier of the insulating film and are injected into the floating gate. Thus the condition in which electrons are injected into the floating gate is the write condition.
However, when, to reduce the size of the EPROM cell, the channel length L is shortened, a high electric field is generated in the vicinity of the drain, not only on applying high voltage in a write operation as described above, but even on executing a read operation, for which a comparatively low voltage is used. Such generation of high electric field during a read operation causes change of the amount of stored charges in the floating gate of the memory cell, which may even destroy the stored data.
In an attempt to avoid such spurious operation occurring when there is a read operation, the memory cell construction shown in FIG. 1 could be considered, for example.
In this Figure, reference numeral 111 designates a P type silicon substrate, reference numerals 112 and 113 designate N.sup.+ diffusion layers constituting a source and drain, respectively. Reference number 114 designates a gate insulating film. Reference numeral 115 designates a floating gate, 116 is a control gate, 117 is a source electrode, and 118 is a drain electrode.
In a semiconductor memory device constructed as above, N.sup.- diffusion layers 121 and 131 are respectively formed adjacent the respective channel formation regions of N.sup.+ diffusion layers 112 and 113 constituting the source and drain.
Thus, formation of N.sup.- diffusion layer 131 reduces the electric field in the drain region so that the aforementioned type of spurious operation could be prevented from occurring when a read operation takes place. However, such a cell construction using a lightly doped region (N.sup.- diffusion region 131) is subject to a serious drawback, in that it has a poor write characteristic. The reason for this is that, since the drain electric field is lowered by N.sup.- diffusion layer 131, the electrons running in the channel region cannot be given sufficient energy, so the efficiency with which they are injected into floating gate 115 is diminished.